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? semiconductor components industries, llc, 2015 september, 2015 ? rev. 5 1 publication order number: tcc?106/d TCC-106 six-output ptic control ic introduction on semiconductor?s ptic controller ic is a six?output high?voltage digital to analog control ic specifically designed to control and bias on semiconductor?s passive tunable integrated circuits (ptics). these tunable capacitive circuits are intended for use in mobile phones and dedicated rf tuning applications. the implementation of on semiconductor?s tunable circu its in mobile phones enables significant improvement in terms of antenna radiated performance. the tunable capacitors are controlled through a bias voltage ranging from 2 v to 20 v. the tcc?106 high?voltage ptic control ic has been specifically designed to cover this need, providing six independent high?voltage outputs that control up to six different tunable ptics in parallel. the device is fully controlled through a multi?protocol digital interface. key features ? controls on semiconductor?s ptic tunable capacitors ? compliant with timing needs of cellular and other wireless system requirements ? integrated boost converter with 6 programmable outputs (up to 24 v) ? low power consumption ? auto?detection of spi (30? or 32?bit) or mipi rffe interfaces (1.2 v or 1.8 v) ? available in wlcsp (rdl ball arrays) and for stand?alone or module integration ? this is a pb?free device typical applications ? multi?band, multi?standard, advanced and simple mobile phones ? tunable antenna matching networks ? compatible with closed?loop and open?loop antenna tuner applications www. onsemi.com see detailed ordering and shipping information in the package dimensions section on page 23 of this data sheet. ordering information marking diagram rdl ball array case 567hl rdl tc6x alyw tc6 = product code x = mipi id a = assembly location l = wafer lot code y = year code w = week code o = pin 1 marker
tcc?106 www. onsemi.com 2 figure 1. control ic functional block diagram 7?bit dac vio gndio avdd l_boost vhv vreg gnd_boost cs clk data trig outa otp level shifter vio por vreg por start reference interface registers booster outb outc regulator 4 bit dac bandgap gnda atest vio_on por_vreg 8 8 8 ibias_start/vref_start vio avdd vreg vhv outd oute outf 8 8 8 idb0 7?bit dac 7?bit dac 7?bit dac 7?bit dac 7?bit dac
tcc?106 www. onsemi.com 3 rdl pin out table 1. pad descriptions bump name type description max voltage (note 1) rdl 1 l_boost aoh boost inductor 25 b4 2 avdd p analog supply 5.5 b3 3 gnda p analog ground 0 c3 4 trig dio trigger signal input (note 2) vio c4 5 clk di mipi rffe / spi clock vio d4 6 cs di chip select for spi vio d3 7 data dio digital io (spi and mipi rffe) vio e4 8 vio p digital io supply 3 e3 9 idb0 di mipi rffe id bit 0 (note 3) vio c2 10 gndio p digital io ground vio d2 11 outa aoh high voltage output a vhv e2 12 outb aoh high voltage output b vhv e1 13 outc aoh high voltage output c vhv d1 14 outd aoh high voltage output d vhv c1 15 oute aoh high voltage output e vhv b1 16 outf aoh high voltage output f vhv a1 17 atest ao analog test out (note 4) vreg b2 18 vreg ao regulator output 3.6 a2 19 gnd_boost p ground for booster 0 a3 20 vhv aoh / aih boost high voltage can be forced externally 25 a4 1. for information only. 2. to be grounded when not in use. 3. this pin has to be connected to either gndio or vio level, even if only spi protocol is used. never let it float. 4. to be grounded in normal operation. electrical performance specifications table 2. absolute maximum ratings symbol parameter rating unit avdd analog supply voltage ?0.3 to +6.0 v vio io reference supply voltage ?0.3 to +3.6 v v i/o input voltage logic lines (data, clk, cs) ?0.3 to vio+0.3 v v hvh vhv maximum voltage ?0.3 to 30 v v esd (hbm) human body model, jesd22?a114, all i/o 2,000 v v esd (mm) machine model, jesd22?a115 200 v t stg storage temperature ?55 to +150 c t amb_op_max max operating ambient temperature without damage +110 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
tcc?106 www. onsemi.com 4 table 3. recomended operating conditions symbol parameter rating unit min typ max t amb_ op operating ambient temperature ?30 ? +85 c t j_ op operating junction temperature ?30 ? +125 c avdd analog supply voltage 2.3 ? 5.5 v vio io reference supply voltage 1.1 ? 3.0 v table 4. dc characteristics (t a = ?30 to +85 c; v outx = 15 v for each output; 2.3 v tcc?106 www. onsemi.com 5 table 5. boost converter characteristics (avdd from 2.3 v to 5.5 v; vio from 1.1 v to 3.0 v; t a = ?30 to +85 c; c hv = 22 nf; l boost = 15 h; unless otherwise specified) symbol parameter conditions min typ max unit vhv_min minimum programmable output volt- age (average), dac boost = 0h active mode ? 9 ? v vhv_max maximum programmable output volt- age (average), dac boost = fh active mode ? 24 ? resolution boost voltage resolution 4?bit dac ? 1 ? i l_ boost_ limit inductor current limit ? 200 ? ma table 6. analog outputs (out a, out b, out c) (avdd from 2.3 v to 5.5 v; vio from 1.1 v to 3.0 v; vhv = 24 v; t a = ?30 to +85 c; rload = unless otherwise specified) parameter description min typ max unit comment shutdown mode z out out a, out b, out c , out d, out e,out f output impedance 7 ? ? megaohm dac disabled active mode v oh maximum output voltage 22.0 ? ? v dac a, b, c, d, e or f = 7fh, dac boost = fh, i oh <10 a v ol minimum output voltage ? ? 1 v dac a, b c, d, e or f = 01h, dac boost = 0h to fh, i oh <10 a slew rate ? 6.5 10 s 2 v to 20 v step, measured at v out = 15.2 v, r load = equivalent series load of 2.7 kohm and 5.6 nf, turbo enabled r pd out a, out b, out c, out d, out e, out f set in pull?down mode ? ? 800 ohm dac a, b c, d, e or f = 00h, dac boost = 0h to fh, selected output(s) is disabled resolution voltage resolution (1?bit) ? 188 ? mv (1 lsb = 1?bit) v offset zero scale, least squared best fit ?1 ? +1 lsb error ?3.0 ? +3.0 %v out over 2 v ? 20 v v o range dnl differential non?linearity least squared best fit ?0.9 ? +0.9 lsb over 2 v ? 20 v v o range inl integral non?linearity least squared best fit ?1 ? +1 lsb over 2 v ? 20 v v o range i sc over current protection ? 35 65 ma any dac output shorted to ground v ripple output ripple with all outputs at steady state ? ? 40 mv rms over 2 v ? 20 v for vhv = 23.5 v
tcc?106 www. onsemi.com 6 theory of operation overview the control ic outputs are directly controlled by programming the six dacs (dac a, dac b, dac c, dac d, dac e and dac f) through the digital interface. the dac stages are driven from a reference voltage, generating an analog output voltage driving a high?voltage amplifier supplied from the boost converter (see figure 1 ? control ic functional block diagram). the control ic output voltages are scaled from 0 v to 24 v, with 128 steps of 188 mv (2 v x 24 v / 255 v = 0.188235 v). the nominal control ic output can be approximated to 188 mv x (dac value). for performance optimization the boost output voltage (vhv) can be programmed to levels between 9 v and 24 v via the dac_boost register (4 bits with 1 v steps). the startup default level for the boosted voltage is vhv = 24 v. for proper operation and to avoid saturation of the output devices and noise issues it is recommended to operate the boosted vhv voltage at least 2 v above the highest programmed v out voltage of any of the six outputs. when the dac output value is set to 00h the corresponding output is disabled and the output is pulled to gnd through an effective impedance of less than 800 ohms. operating modes the following operating modes are available: 1. shutdown mode: all circuit blocks are off, the dac outputs are disabled and placed in high z state and current consumption is limited to minimal leakage current. the shutdown mode is entered upon initial application of avdd or upon vio being placed in the low state. the contents of the registers are not maintained in shutdown mode. 2. startup mode: startup is only a transitory mode. startup mode is entered upon a vio high state. in startup mode all registers are reset to their default states, the digital interface is functional, the boost converter is activated, outputs out a, out b, out c, out d, out e and out f are disabled and the dac outputs are placed in a high z state. control software can request a full hardware and register reset of the tcc?106 by sending an appropriate pwr_mode command to direct the chip from either the active mode or the low power mode to the startup mode. from the startup mode the device automatically proceeds to the active mode. 3. active mode: all blocks of the tcc?106 are activated and the dac outputs are fully controlled through the digital interface, dacs remain off until enabled. the dac settings can be dynamically modified and the hv outputs will be adjusted according to the specified timing diagrams. each dac can be individually controlled and/or switched off according to application requirements. active mode is automatically entered from the startup mode. active mode can also be entered from the low power mode under control software command. 4. low power mode: in low power mode the serial interface stays enabled, the dac outputs are disabled and are placed in a high z state and the boost voltage circuit is disabled. control software can request to enter the low power mode from the active mode by sending an appropriate pwr_mode command. the contents of all registers are maintained in the low power mode. shutdown startup (registers reset) active low power (user defined) pwr_mode = 0b10 vdda = 0 figure 2. modes of operation battery insertion (user defined) pwr_mode = 0b01 automatic vio = high vio = low vio = low pwr_mode = 0b00 pwr_mode = 0b01
tcc?106 www. onsemi.com 7 avdd power?on reset (por) upon application of avdd the tcc?106 will be in shutdown mode. all circuit blocks are off and the chip draws only minimal leakage current. vio power?on reset and startup conditions a high level on vio places the chip in startup mode which provides a por to the tcc?106. por resets all registers to their default settings as described in table 8. vio por also resets the serial interface circuitry. por is not a brown?out detector and vio needs to be brought back to a low level to enable the por to trigger again. table 7. vio power?on reset and startup register default state for vio por comment dac boost [1111] vhv = 24 v power mode [01]>[00] transitions from shutdown to startup and then automatically to active mode dac enable [000000] v out a, b, c, d, e and f disabled dac a output in high?z mode dac b output in high?z mode dac c output in high?z mode dac d output in high?z mode dac e output in high?z mode dac f output in high?z mode vio shutdown a low level at any time on vio places the chip in shutdown mode in which all circuit blocks are off. the contents of the registers are not maintained in shutdown mode. table 8. vio thresholds (avdd from 2.3 v to 5.5 v; t a = ?30 to +85 c unless otherwise specified) parameter description min typ max unit comments viorst vio low threshold ? ? 0.2 v when vio is lowered below this threshold level the chip is reset and placed into the shutdown state power supply sequencing the avdd input is typically directly supplied from the battery an d thus is the first on. after avdd is applied and before vio is applied to the chip, all circuits are in the shutdown stat e and draw minimum leakage cu rrents. upon application of vio, the chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface . table 9. timing (avdd from 2.3 v to 5.5 v; vio from 1.1 v to 3.0 v; t a = ?30 to +85 c; out a, out b, out c, out d, out e & out f; chv = 22 nf; l boost = 15 h; vhv = 20 v; t urbo?charge mode off unless otherwise specified) parameter description min typ max unit comments t por_ vreg internal bias settling time from shutdown to active mode ? 50 120 s for info only t boost_ start time to charge chv @ 95% of set vhv ? 130 ? s for info only t sd_ to_ act startup time from shutdown to active mode ? 180 300 s t set+ output a, b, c, d, e, f positive settling time to within 5% of the delta voltage, equivalent series load of 2.7 kohm and 5.6 nf, v out from 2 v to 20 v; 0bh (11d) to 55h (85d) ? 50 60 s voltage settling time connected on v out a, b, c, d, e, f t set? output a, b, c, d, e, f negative settling time to within 5% of the delta voltage, equivalent series load of 2.7 kohm and 5.6 nf, v out from 20 v to 2 v; 55h (85d) to 0bh (11d) ? 50 60 s voltage settling time connected on v out a, b, c, d, e, f t set+ output a, b, c, d, e, f positive settling time with turbo ? 35 ? s voltage settling time connected on v out a, b, c, d, e, f t set? output a, b, c, d, e, f negative settling time with turbo ? 35 ? s voltage settling time connected on v out a, b, c, d, e, f
tcc?106 www. onsemi.com 8 figure 3. output settling diagram figure 4. startup timing diagram
tcc?106 www. onsemi.com 9 boost control the tcc?106 integrates an asynchronous current control boost converter. it operates in a discontinuous mode and features spread?spectrum circuitry for electro?magnetic interference (emi) reduction. the average boost clock is 2 mhz and the clock is spread between 0.8 mhz and 3.2 mhz. boost output voltage (vhv) control principle the asynchronous control starts the boost converter as soon as the vhv voltage drops below the reference set by the 4?bit dac and stops the boost converter when the vhv voltage rises above the reference again. due to the slow response time of the control loop, the vhv voltage may drop below the set voltage before the control loop compensates for it. in the same manner, vhv can rise higher than the set value. this effect may reduce the maximum output voltage available. please refer to figure 6 below. the asynchronous control reduces switching losses and improves the output (vhv) regulation of the dc/dc converter under light load, particularly in the situation where the tcc?106 only maintains the output voltages to fixed values. set vhv figure 5. vhv voltage waveform vhv time delay delay chv discharge delay chv recharge boost running high impedance (high z) feature in shutdown mode the out pins are set to a high impedance mode (high z). following is the principle of operation for the control ic: 1. the dac output voltage v out is defined by: v out dac code 255 24 v 2 (eq. 1) 2. the voltage vhv defines the maximum supply voltage of the dac supply output regulator and is set by a 4?bit control. 3. the maximum dac dc output voltage v out is limited to (vhv ? 2 v). 4. the minimum output dac voltage v out is 1.0 v max. figure 6. dac output range example a figure 7. dac output range example b digital interface the control ic is fully controlled through a digital interface (data, clk, cs). the digital interface auto? matically detects and responds to mipi rffe interface commands, 3?wire 30?bit serial interface commands or 3?wire 32?bit serial interface commands. auto?detection is accomplished on a frame by frame basis. the digital interface is described in the following sections of this document, for detailed programming instructions please refer to the programming guide, available by contacting on semiconductor. 3?wire serial interface the 3?wire serial interface operates in a synchronous write?only 3?wire slave mode. 30?bit or 32?bit message length is automatically detected for each frame. if cs changes state before all bits are received then all data bits are ignored. data is transmitted most significant bit first and data is latched on the rising edge of clk. commands are latched on the falling edge of cs.
tcc?106 www. onsemi.com 10 table 10. 3?wire serial interface specification (t a = ?30 to +85 c; 2.3 v tcc?106 www. onsemi.com 11 figure 8. 3?wire serial interface signal timing spi frame length decoding 30?bit or 32?bit frame length is automatically detected. the length of the frame is defined by the number of clock rising edges while cs is kept high. the tcc?106 will not respond to a spi command if the length of the frame is not exactly 30 bits or 32 bits. spi registers are write only. spi frame structure table 11. 32 bits frame: address decoding (1, 2, 3, 4, 5 or 6 outputs) h0 h1 r/w a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 0 1 0 1 0 0 1 0 0 x x x x x on semiconductor header r/w device id specific device id register address for operation table 12. 30 bits frame: address decoding (1, 2, 3, 4, 5 or 6 outputs) r/w a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 0 1 0 0 1 0 0 x x x x x r/w device id specific device id register address for operation table 13. 3?wire serial interface address map a4 a3 a2 a1 a0 data[15:8] data[7:0] 0 0 0 0 0 turbo?charge settings for dac a, b, c dac c 0 0 0 0 1 dac b dac a 0 0 0 1 0 turbo?charge settings for dac d, e, f dac f 0 0 0 1 1 dac e dac d 0 0 1 0 0 turbo?charge delay parameters for dac a, b, c turbo threshold delay settings for a, b, c 0 0 1 0 1 turbo?charge delay parameters for dac d, e, f turbo threshold delay settings for a, b, c 1 0 0 0 0 mode select + control ic setup
tcc?106 www. onsemi.com 12 table 13. 3?wire serial interface address map 1 0 0 1 0 reserved reserved to 1 1 1 1 1 turbo?charge mode the tcc?106 control ic has a turbo?char ge mode that significantly shortens the system settling time when changing programming voltages. in turbo?char ge mode the dac output target voltage is temporarily set to either a delta voltage above or a delta voltage below the actual desired target for the tcdly time. it is recommended that v hv be set to 24 v when using t urbo?charge mode. glide mode unlike turbo mode, which is intended to reduce the charging time, the glide mode extends the transition time of each dac output. each dac has an individual control for turbo mode, glide mode or regular voltage switching. the glide mode can be enabled for a particular dac through the index register, by setting dac state to ?1? when glide mode is enabled, turbo mode is off for a particular dac, but one dac can be gliding while the other is turbo. during glide mode the output voltage of a dac is either increased or dec reased to its set end point, in max 255 steps, where each dac time step can be programmed between 2 s to 64 s. for programming the glide mode refer to the application note (coming soon). a programming input is not required to maintain a glide transition, all step controls are maintained by the part. only the inputs to define the glide need to be programmed. rf front?end control interface (mipi rffe interface) the tcc?106 is a read/write slave device which is fully compliant to the mipi alliance specification for rf front?end control interface (rffe) version 1.10.00 26 july 2011. this device is rated at full?speed operation for 1.65 v tcc?106 www. onsemi.com 13 table 14. mipi rffe interface specification (t a = ?30 to +85 c; 2.3 v tcc?106 www. onsemi.com 14 the control ic contains twenty?four 8?bit registers. register content is described in table 15. some additional registers implemented as provision, are not described in this document. table 15. mipi rffe address map register address description purpose access type size (bits) 0x00 dac configuration (enable mask) high voltage output enable mask write 7 0x01 turbo register dac a, b & c turbo?charge configuration dac a, b & c write 8 0x02 dac a register out a value [6:0], turbo index [7]** write 8 0x03 dac b register out b value [6:0], turbo index [7]** write 8 0x04 dac c register out c value [6:0], turbo index [7]** write 8 0x05 turbo register dac d, e & f turbo?charge configuration dac d,e & f write 8 0x06 dac d register out d value [6:0], turbo index [7]** write 8 0x07 dac e register out e value [6:0], turbo index [7]** write 8 0x08 dac f register out f value [6:0], turbo index [7]** write 8 0x10 dac boost (vhv) settings for the boost high voltage write 8 0x11 trigger register trigger configuration write 8 0x12 turbo?charge delay dac a, b, c turbo?charge delay steps dac a, b, c write 8 0x13 turbo?charge delay dac a, b, c turbo?charge delay, multiplication dac a, b, c write 8 0x14 turbo?charge delay dac d, e, f turbo?charge delay steps dac d, e, f write 8 0x15 turbo?charge delay dac d, e, f turbo?charge delay multiplication dac d, e, f write 8 0x1c power mode and trigger register power mode & trigger control pwr_mode [7:6] trig_reg [5:0] write 8 0x1d product id register product number * hard coded into asic write 8 0x1e manufacturer id register mn (10 bits long) manufacturer id[7:0] hard coded into asic write 8 0x1f unique slave identifier register (usid) spare [7:6] [5,4] = manufacturer id [9:8] usid [3:0] write 8 *the second least significant bit can be programmed in otp during manufacture ** the details for configuration of turbo mode should be ascertained from the programming guide, available from on semiconducto r configuration settings table 16. dac configuration (enable mask) at [0x00] defaults shown as (x) bit 6 (1) bit 5 (0) bit 4 (0) bit 3 (0) bit 2 (0) bit 1 (0) bit 0 (0) sse dac e dac f dac a dac b dac c dac d sse = 0 spread spectrum disabled, sse = 1 spread spectrum enabled (default), this controls the average boost clock which is nominally 2 mhz and spread between 0.8 mhz and 3.2 mhz when enabled (default). the hardware does not limit driving more than three dacs at the same time, however it is recommended to have max three dacs changing outputs at one time, no restrictions exist as to which three.
tcc?106 www. onsemi.com 15 table 17. dac mode setup: dac enable bit3 bit2 bit1 dac a dac b dac c 0 0 0 off off off (default) 0 0 1 off off enabled 0 1 0 off enabled off 0 1 1 off enabled enabled 1 0 0 enabled off off 1 0 1 enabled off enabled 1 1 0 enabled enabled off 1 1 1 enabled enabled enabled table 18. dac mode setup: dac enable bit5 bit4 bit0 dac e dac f dac d 0 0 0 off off off (default) 0 0 1 off off enabled 0 1 0 off enabled off 0 1 1 off enabled enabled 1 0 0 enabled off off 1 0 1 enabled off enabled 1 1 0 enabled enabled off 1 1 1 enabled enabled enabled table 19. boost dac mode setup (vhv) at [0x10] (note 5) bit 7* bit 6* bit 5* bit 4 bit 3 bit 2 bit 1 bit 0 vhv (v) 0 0 0 1 0 0 0 0 9 0 0 0 1 0 0 0 1 10 0 0 0 1 0 0 1 0 11 0 0 0 1 0 0 1 1 12 0 0 0 1 0 1 0 0 13 0 0 0 1 0 1 0 1 14 0 0 0 1 0 1 1 0 15 0 0 0 1 0 1 1 1 16 0 0 0 1 1 0 0 0 17 0 0 0 1 1 0 0 1 18 0 0 0 1 1 0 1 0 19 0 0 0 1 1 0 1 1 20 0 0 0 1 1 1 0 0 21 0 0 0 1 1 1 0 1 22 0 0 0 1 1 1 1 0 23 0 0 0 1 1 1 1 1 24 (default) 5. bit 4 is fixed at logic 1 for reverse software compatibility *indicates reserved bits
tcc?106 www. onsemi.com 16 mipi rffe trig operation the mipi rffe trigger mode can be used as a synchronization signal to ensure that new dac settings are applied to the outputs at appropriate times in the overall transceiver system. when the mipi rffe trig function is enabled via [0x11] bit 4 the requested dac voltage levels are set up in the shadow registers and not transferred to the destination registers until the trigger condition is met. in this manner the change in output voltage levels are synchronized with the mipi rffe trig command. if multiple dac voltage level requests are received before the trig event occurs, only the last fully received dac output voltage level will be applied to the outputs. the trigger configuration also provides for an additional external trig pin to be used as a synchronization signal. the external trig is independent from the built?in triggers available within the mipi rffe interface. when the trig input pin is enabled via [0x11] bit 4 the requested dac voltage levels are set up in the shadow registers and are not transferred to the destination registers until the external trigger condition is met. in this manner the change in output voltage levels are synchronized with the external trig event. the external trig input is referenced to vio. to improve interfacing options the polarity of external trig is programmable via [0x11] bit 1. if the external trigger function is not needed in the application, the trig pin should be grounded and the trig function disabled. when trig pin is disabled by register [0x11] ?trig select? = ?1? (default) and register [0x10] ?trigger mask 0, 1, 2? = ?1?: ? the requested dac voltage levels for dac a, b, c are applied to the outputs all together at the same time, after dac c value is written. this event will not affect the outputs of dac d, e, f. ? the requested dac voltage levels for dac d, e, f are applied to the outputs all together at the same time, after dac f value is written. this event will not affect the outputs of dac a, b, c. ? optionally a configuration register can select the last dac to be written in order to trigger internally the update of all six dacs at the same time. for example the configuration register can select that a write to dac b value will trigger internally the update of all six dacs outputs. table 20. trigger configuration at [0x11] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res* 0 res* 0 res* 0 trig select 0 = ext trig pin 1 = rffe trigger reserved 0 trig edge 0 = active falling 1 = active rising mask ext trig 1 = mask trig pin *reserved bits table 21. external trigger configuration bit setting at [0x11] bit 4 bit 3 bit 2 bit 1 bit 0 description 0 ? ? x 0 external trigger pin is enabled. sending the rffe message will load a ?shadow? register only. only upon an active signal on external trig pin are the output re- gisters loaded with the new voltage settings which are then applied to the outputs. 1 ? ? x x the mipi rffe trigger is enabled (default) 0 ? ? 0 0 external trig pin signal is active falling 0 ? ? 1 0 external trig pin signal is active rising (default) x ? ? x 0 external trigger pin is not masked x ? ? x 1 mask external trigger pin (default) table 22. power mode and trigger register [0x1c] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pm1 pm0 trigger mask 2 trigger mask 1 trigger mask 0 trigger 2 trigger 1 trigger 0 writing a logic one (?1?) to the bits 0, 1 or 2 (trigger 0, 1 or 2) moves data from the shadow registers into the destination registers. default for bit 0, 1 and 2 is logic low. if trigger mask bit 0, 1 or 2 is set (?1?) the trigger 0, 1 or 2 are disabled respectively and the data goes directly to the destination register. default for bit 3, 4 and 5 is logic low. all three triggers behave in the same way as the external pin trig. when each of these triggers is set using the mipi rffe interface the results are the same as when an active edge is applied to the trig pin when external pin trig is selected
tcc?106 www. onsemi.com 17 table 23. power mode bit setting in register [0x1c] pm1 pm0 state description 0 0 active boost control active, vhv set by digital interface v out a, b, c, d, e, f enabled and controlled by digital interface (default) 0 1 startup boost control active, vhv set by digital interface v out a, b, c, d, e, f disabled 1 0 low power digital interface is active while all other circuits are in low power mode 1 1 reserved state of hardware does not change command sequences ? register 0 write (used to access the register 0 dac configuration ? enable mask). register 0 can be also be accessed using register write or/and extended register write. ? register write (used to access only one register at the time) ? extended register write (used to access a group of contiguous registers with one command) register 0 write command sequence the command sequence starts with a sequence start condition (ssc) which is followed by the register 0 write command frame. this frame contains the slave address, a logic one, and the seven bit word that will be written to register 0. the command sequence is depicted below. figure 12. register 0 write command sequence table 24. mipi rffe command frame for register 0 write command sequence description ssc command frame bp sse & dac configuration 1 0 sa [3,0] 1 sse dac_e dac_f dac_a dac_b dac_c dac_d p bp
tcc?106 www. onsemi.com 18 register write command sequence the write register command sequence may be used to access each register (addresses 0?31). figure 13. register write command sequence table 25. mipi rffe command frame for register write command sentence description ssc command frame data frame bp turbo?charge settings 1 0 sa [3,0] 0 1 0 0 0 0 0 1 p tc_indx_l [7:0] p bp register write dac a 1 0 sa [3,0] 0 1 0 0 0 0 1 0 p tc_indx_l [8] & dac_a [6:0] p bp register write dac b 1 0 sa [3,0] 0 1 0 0 0 0 1 1 p tc_indx_l [9] & dac_b [6:0] p bp register write dac c 1 0 sa [3,0] 0 1 0 0 0 1 0 0 p tc_indx_l [10] & dac_c [6:0] p bp table 26. mipi rffe command frame for register write command sentence description ssc command frame data frame bp turbo?charge settings 1 0 sa [3,0] 0 1 0 0 0 1 0 1 p tc_indx_u [7:0] p bp register write dac d 1 0 sa [3,0] 0 1 0 0 0 1 1 0 p tc_indx_u [8] & dac_d [6:0] p bp register write dac e 1 0 sa [3,0] 0 1 0 0 0 1 1 1 p tc_indx_u [9] & dac_e [6:0] p bp register write dac f 1 0 sa [3,0] 0 1 0 0 1 0 0 0 p tc_indx_u [10] & dac_f [6:0] p bp
tcc?106 www. onsemi.com 19 extended register write command sequence in order to access more than one register in one sequence this message could be used. most commonly it will be used for loading three dac registers at the same time. the four lsbs of the extended register write command frame determine the number of bytes that will be written by the command sequence. a value of 0b0000 would write one byte and a value of 0b1111 would write 16 bytes. if more than one byte is to be written, the register address in the command sequence contains the address of the first extended register that will be written to and the slave?s local extended register address shall be automatically incremented by one for each byte written up to address 0x1f, starting from the address indicated in the address frame. figure 14. extended register write command sequence
tcc?106 www. onsemi.com 20 table 27. extended register write to update dac a, b, c (note 6) description ssc command frame address frame extended register write tc_indx_l and dac a, b, c op code p p 1 0 sa [3,0] 0 0 0 0 0 0 1 1 p 0 0 0 0 0 0 0 1 p data frame data frame data frame data frame bp p p p p bp turbo?charge p dac_a [7,0] p dac_b [7,0] p dac_c [7,0] p bp table 28. extended register write to update dac d, e, f (note 6) description ssc command frame address frame extended register write tc_indx_u and dac d, e, f op code p p 1 0 sa [3,0] 0 0 0 0 0 0 1 1 p 0 0 0 0 0 1 0 1 p data frame data frame data frame data frame bp p p p p bp turbo?charge p dac_d [7,0] p dac_e [7,0] p dac_f [7,0] p bp 6. the six dacs can be updated either all together in the same time by using one extended register write command of 8 bytes, or separately by using two extended register write commands of 4 bytes each, where one command is to update dac a, b, c and the other command to update dac d, e, f. figure 15. register read command sequence table 29. register read command description ssc command frame read mipi?rffe status register 1 0 sa[3:0] 0 1 1 1 1 0 1 0 p bp description data frame read mipi?rffe status register (continued) 0 cfpe cle afpe dfpe rure wure bge bp
tcc?106 www. onsemi.com 21 following picture shows tcc?106 and all the necessary external components figure 16. tcc?106 with external components table 30. recommended external bom component description nominal value package recommended p/n c boost boost supply capacitor, 10 v 1 f 0402 tdk: c1005x5r1a105k l boost boost inductor 15 h 0603 abco: lps181210t?150m, sunlord sph201610h150mt r filt filtering resistor, 5% 3.3 ohms 0402 vishay : crcw04023r30jned c vio v io supply decoupling, 10 v 100 nf 0201 murata: grm033r61a104me15d c avdd v avdd supply decoupling, 10 v 1 f 0402 tdk: c1005x5r1a105k c vreg v vreg supply decoupling, 10 v 220 nf 0201 tdk: c0603x5r1a224m c hv boost tank capacitor, 50 v 47 nf 1005 murata: grm155c71h473ke19 c daca,b,c,d,e,f decoupling capacitor, 50 v (note 7) 100 pf 0201 murata: grm0335c1h101jd01d 7. recommended for noise reduction only ? not essential
tcc?106 www. onsemi.com 22 mechanical description: ball array package 530 m 530 m 400 m 400 m 400 m 400 m 400 m 400 m 500 m 500 m 250 m dia figure 17. ball array package ? top view pb-free (96.8% sn/2.6% ag/0.6% cu) tc6 = product code x = mipi id (see mipi version table) 7 = assembly location l = wafer lot code y = year code w = week code ? = pin 1 marker a=0 b=1 mipi rffe id bit 1 2250 m 10 m 2600 m 10 m tc6x 7lyw a1 a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 d1 d2 d3 d4 e1 e2 e3 e4 580 m 380 m 25 m 200 m 20 m 400 m note: die dimensions include an assumed 60 m wide sawing kerf, this kerf width is subject to change without notice.
tcc?106 www. onsemi.com 23 tape & reel dimensions figure 18. wlcsp carrier tape drawings table 31. ordering information device package shipping ? tcc?106a?rt rdl (pb?free) 3000 / tape & reel tcc?106b?rt rdl (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
tcc?106 www. onsemi.com 24 package dimensions wlcsp20, 2.58x2.23 case 567hl issue o seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 2.58 bsc e b 0.23 0.29 e 0.40 bsc 0.65 e d a b pin a1 reference e a 0.05 b c 0.03 c 0.08 c 20x b 4 c b a 0.10 c a1 a c 0.18 0.22 2.23 bsc 0.25 20x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.05 c 2x top view side view bottom view note 3 e a3 0.38 ref recommended package outline 123 pitch d e pitch a1 e/2 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 tcc?106/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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